Vystem 0.2

shelter/lib/include/devs/acpi.h

@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_ACPI_H
+#define SH_LIB_ACPI_H
+#include "std/stdlib.h"
+// ACPI v1 RSDP structure
+typedef struct {
+  sh_uint8 signature[8];
+  sh_uint8 checksum;
+  sh_uint8 oem_id[6];
+  sh_uint8 revision;
+  sh_uint32 rsdt_address;
+} sh_acpi_RSDP_V1;
+// ACPI v2 RSDP structure
+typedef struct {
+  sh_acpi_RSDP_V1 first_part;
+  sh_uint32 length;
+  sh_uint64 xsdt_address;
+  sh_uint8 extended_checksum;
+  sh_uint8 reserved[3];
+} sh_acpi_RSDP_V2;
+// ACPI pointers root structure
+typedef struct {
+  sh_uint64 rsdt;
+  sh_uint64 xsdt; // set to 0 if ACPI v2 isn't supported
+} sh_apci_ACPI_POINTERS_ROOT;
+// ACPI XSDT header
+typedef struct {
+  char signature[4];
+  sh_uint32 length;
+  sh_uint8 revision;
+  sh_uint8 checksum;
+  char oem_id[6];
+  char oem_table_id[8];
+  sh_uint32 oem_revision;
+  sh_uint32 creator_id;
+  sh_uint32 creator_revision;
+} sh_acpi_ACPI_XSDT_HEADER;
+// ACPI XSTD body
+typedef struct {
+  sh_uint64 *entries;
+  sh_uint64 entry_count;
+} sh_acpi_ACPI_XSDT_BODY;
+// ACPI tables list
+typedef struct {
+  sh_uint64 madt_physical_address;
+} sh_acpi_ACPI_TABLES;
+// ACPI table header
+typedef struct {
+  char signature[4];
+  sh_uint32 length;
+  sh_uint8 revision;
+  sh_uint8 checksum;
+  char oem_id[6];
+  char oem_table_id[8];
+  sh_uint32 oem_revision;
+  sh_uint32 creator_id;
+  sh_uint32 creator_revision;
+} sh_acpi_TABLE_HEADER;
+// Try to obtain ACPI root pointer
+SH_STATUS sh_acpi_parse_rsdp(sh_uint64 rsdp,sh_uint8 acpi_ver,sh_apci_ACPI_POINTERS_ROOT *out);
+// Parse XSDT header and ensure that all entries are mapped
+SH_STATUS sh_acpi_parse_xsdt(sh_uint64 xsdt,sh_acpi_ACPI_XSDT_BODY *xsdt_body);
+// Parse XSDT entries, ensure that all the headers of each table is mapped and sort all entries into their respectives fields inside acpi_tables. Doesn't parse each table header
+SH_STATUS sh_acpi_parse_tables(sh_acpi_ACPI_XSDT_BODY *xsdt_body,sh_acpi_ACPI_TABLES *acpi_tables);
+#endif

shelter/lib/include/devs/acpi_tables/madt.h

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_ACPI_MADT_H
+#define SH_LIB_ACPI_MADT_H
+#include "std/stdlib.h"
+// MADT header structure
+typedef struct {
+  char signature[4];
+  sh_uint32 length;
+  sh_uint8 revision;
+  sh_uint8 checksum;
+  char oem_id[6];
+  char oem_table_id[8];
+  sh_uint32 oem_revision;
+  sh_uint32 creator_id;
+  sh_uint32 creator_revision;
+} sh_acpi_madt_TABLE_HEADER;
+// MADT structure
+typedef struct {
+  sh_acpi_madt_TABLE_HEADER header;
+  sh_uint32 local_apic_address;
+  sh_uint32 flags;
+} sh_acpi_madt_MADT;
+// MADT entry header structure
+typedef struct {
+  sh_uint8 type;
+  sh_uint8 length;
+} sh_acpi_madt_ENTRY_HEADER;
+// Local APIC structure
+typedef struct {
+  sh_acpi_madt_ENTRY_HEADER header;
+  sh_uint8 acpi_processor_id;
+  sh_uint8 apic_id;
+  sh_uint32 flags;
+} sh_acpi_madt_LAPIC;
+// IO APIC structure
+typedef struct {
+  sh_acpi_madt_ENTRY_HEADER header;
+  sh_uint8 ioapic_id;
+  sh_uint8 reserved;
+  sh_uint32 ioapic_address;
+  sh_uint32 global_system_interrupt_base;
+} sh_acpi_madt_IOAPIC;
+// Interrupt source override structure
+typedef struct {
+  sh_acpi_madt_ENTRY_HEADER header;
+  sh_uint8 bus;
+  sh_uint8 source;
+  sh_uint32 gsi;
+  sh_uint16 flags;
+} sh_acpi_madt_ISO;
+// Parse MADT table
+SH_STATUS sh_acpi_madt_parse(sh_uint64 madt_ptr);
+#endif

shelter/lib/include/devs/apic/ioapic.h

@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_IOAPIC_H
+#define SH_LIB_IOAPIC_H
+#include "std/stdlib.h"
+#include "memory/page.h"
+#define SH_IOAPIC_OFFSET_IOREGSEL 0x00
+#define SH_IOAPIC_OFFSET_IOWIN 0x10
+#define SH_IOAPIC_REGISTER_IOAPICID 0x00
+#define SH_IOAPIC_REGISTER_IOAPICVER 0x01
+#define SH_IOAPIC_REGISTER_IOAPICARB 0x02
+#define SH_IOAPIC_REGISTER_IOREDTBL_BASE 0x10
+// IOAPIC device structure
+typedef struct {
+  volatile sh_uint32 *base;
+  sh_uint8 ioapic_id;
+  sh_uint32 gsi_base;
+  sh_uint32 gsi_count; // must be completed by reading the IOAPICVER register in the sh_ioapic_init call
+  sh_SPIN_LOCK lock;
+} sh_ioapic_DEVICE;
+// Initialize an IOAPIC device structure, intented to initialize all IOAPIC devices structures during MADT parsing
+SH_STATUS sh_ioapic_init(sh_uint32 base,sh_uint8 ioapic_id,sh_uint32 gsi_base,sh_ioapic_DEVICE *ioapic);
+// Initialize DevS IOAPIC backend (max_ioapic_id is the max IOAPIC id, not the number of IOAPIC counted)
+SH_STATUS sh_ioapic_init_devs(sh_uint8 max_ioapic_id);
+// Bind a LAPIC device to DevS LAPIC backend
+SH_STATUS sh_ioapic_bind(sh_ioapic_DEVICE *lapic_dev);
+// Return a pointer to an IOAPIC device based on the provided IOAPIC id
+sh_ioapic_DEVICE *sh_ioapic_get_dev_ioapic_id(sh_uint64 ioapic_id);
+#define SH_IOAPIC_IOREDTBL_DELIVERY_FIXED 0b000
+#define SH_IOAPIC_IOREDTBL_DELIVERY_LOWEST_PRIORITY 0b001
+#define SH_IOAPIC_IOREDTBL_DELIVERY_NMI 0b100
+#define SH_IOAPIC_IOREDTBL_DELIVERY_INIT 0b101
+#define SH_IOAPIC_IOREDTBL_DELIVERY_EXTINT 0b111
+#define SH_IOAPIC_IOREDTBL_TRIGGER_EDGE 0b0
+#define SH_IOAPIC_IOREDTBL_TRIGGER_LEVEL 0b1
+#define SH_IOAPIC_IOREDTBL_POLARITY_HIGH 0b0
+#define SH_IOAPIC_IOREDTBL_POLARITY_LOW 0b1
+#define SH_IOAPIC_IOREDTBL_DEST_MODE_PHYSICAL 0b0
+#define SH_IOAPIC_IOREDTBL_DEST_MODE_LOGICAL 0b1
+// IOREDTBL entry structure
+typedef struct {
+  sh_uint32 low;
+  sh_uint32 high;
+} sh_ioapic_IOREDTBL_ENTRY;
+// Create an IOREDTBL entry
+inline sh_ioapic_IOREDTBL_ENTRY sh_ioapic_make_ioredtbl_entry(sh_uint8 vector,sh_uint8 delivery_mode,sh_uint8 destination_mode,sh_uint8 polarity,sh_uint8 trigger_mode,sh_bool mask,sh_uint8 apic_id) {
+  sh_ioapic_IOREDTBL_ENTRY e={0};
+  e.low=(e.low& ~0xFFU)|vector;
+  e.low=(e.low& ~(0x7U<<8))|((delivery_mode&0x7U)<<8);
+  e.low=(e.low& ~(1U<<11))|((destination_mode&0x1U)<<11);
+  e.low=(e.low& ~(1U<<13))|((polarity&0x1U)<<13);
+  e.low=(e.low& ~(1U<<15))|((trigger_mode&0x1U)<<15);
+  e.low=(e.low& ~(1U<<16))|((mask&0x1U)<<16);
+  e.high=(e.high& ~(0xFFU<<24))|((sh_uint32)apic_id<<24);
+  return e;
+}
+// Mask an IOREDTBL entry for the provided GSI
+SH_STATUS sh_ioapic_mask_gsi(sh_ioapic_DEVICE *dev,sh_uint32 gsi);
+// Unmask an IOREDTBL entry for the provided GSI
+SH_STATUS sh_ioapic_unmask_gsi(sh_ioapic_DEVICE *dev,sh_uint32 gsi);
+// Read an IOREDTBL entry for the provided GSI
+SH_STATUS sh_ioapic_read_ioredtbl_entry(sh_ioapic_DEVICE *ioapic_dev,sh_uint32 gsi,sh_ioapic_IOREDTBL_ENTRY *entry);
+// Write an IOREDTBL entry for the provided GSI
+SH_STATUS sh_ioapic_write_ioredtbl_entry(sh_ioapic_DEVICE *ioapic_dev,sh_uint32 gsi,sh_ioapic_IOREDTBL_ENTRY *entry);
+// Mask all IOREDTBL entries for all IOAPIC
+SH_STATUS sh_ioapic_mask_all();
+// Return the IOAPIC device corresponding to the provided GSI
+sh_ioapic_DEVICE *sh_ioapic_get_dev_by_gsi(sh_uint32 gsi);
+// Parse an IOAPIC DevS query
+SH_STATUS sh_ioapic_devs_query(char *sub_path,sh_devs_RESULT *result);
+#endif

shelter/lib/include/devs/apic/lapic.h

@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_LAPIC_H
+#define SH_LIB_LAPIC_H
+#include "std/status.h"
+#include "std/type.h"
+#include "memory/page.h"
+#include "devs/devs.h"
+#define SH_LAPIC_OFFSET_ID 0x020
+#define SH_LAPIC_OFFSET_VERSION 0x030
+#define SH_LAPIC_OFFSET_EOI 0x0B0
+#define SH_LAPIC_OFFSET_SVR 0x0F0
+#define SH_LAPIC_OFFSET_ESR 0x280
+#define SH_LAPIC_OFFSET_ICR_LOW 0x300
+#define SH_LAPIC_OFFSET_ICR_HIGH 0x310
+#define SH_LAPIC_OFFSET_LVT_TIMER 0x320
+#define SH_LAPIC_OFFSET_LVT_ERROR 0x370
+#define SH_LAPIC_OFFSET_TIMER_INIT 0x380
+#define SH_LAPIC_OFFSET_TIMER_CURR 0x390
+#define SH_LAPIC_OFFSET_TIMER_DIV 0x3E0
+#define SH_LAPIC_TIMER_DIVIDER 0x3
+// LAPIC device structure
+typedef struct {
+  volatile sh_uint32 *base;
+  sh_uint8 apic_id;
+  sh_uint8 acpi_processor_id;
+  sh_uint32 flags;
+  sh_uint32 spurious_vector;
+} sh_lapic_DEVICE;
+// Initialize a LAPIC device structure, intented to initialize all LAPIC devices structures during MADT parsing
+SH_STATUS sh_lapic_init(sh_uint64 lapic_phys,sh_uint8 spurious_vector,sh_uint8 apic_id,sh_uint8 apic_processor_id,sh_uint32 flags,sh_lapic_DEVICE *lapic);
+// Initialize LAPIC for this CPU, intended to be used once by each CPU
+SH_STATUS sh_lapic_init_dev(sh_uint8 spurious_vector,sh_lapic_DEVICE *lapic);
+// Initialize DevS LAPIC backend (max_lapic_id is the max LAPIC id, not the number of LAPIC counted)
+SH_STATUS sh_lapic_init_devs(sh_uint16 max_lapic_id,sh_uint16 max_acpi_processor_id);
+// Bind a LAPIC device to DevS LAPIC backend
+SH_STATUS sh_lapic_bind(sh_lapic_DEVICE *lapic_dev);
+// Write 0 in provided LAPIC device EOI register
+void sh_lapic_eoi(sh_lapic_DEVICE *lapic);
+// Return a pointer to a LAPIC device based on the provided APIC id
+sh_lapic_DEVICE *sh_lapic_get_dev_apic_id(sh_uint64 apic_id);
+// Return a pointer to a LAPIC device based on the provided ACPI processor id
+sh_lapic_DEVICE *sh_lapic_get_dev_acpi_cpu_id(sh_uint64 acpi_processor_id);
+// Launch a LAPIC one-shot timer, independantely of the calibrated state of the LAPIC
+SH_STATUS sh_lapic_timer_one_shot(sh_lapic_DEVICE *lapic_dev,sh_uint32 initial_value);
+// Calibrate the LAPIC frequency
+SH_STATUS sh_lapic_calibrate(sh_lapic_DEVICE *lapic_dev,sh_uint64 cpu_freq);
+// Return the LAPIC frequency
+sh_uint64 sh_lapic_get_frequency();
+// Launch a LAPIC one-shot timer, LAPIC frequency need to be set
+SH_STATUS sh_lapic_timer_one_shot_us(sh_lapic_DEVICE *lapic_dev,sh_uint64 microseconds_count);
+// Return LAPIC DevS array
+sh_lapic_DEVICE **sh_lapic_get_by_apic_id_array();
+// Return max LAPIC APIC id
+sh_uint64 sh_lapic_get_max_apic_id();
+// Return max ACPI processor id
+sh_uint64 sh_lapic_get_max_acpi_processor_id();
+// Return LAPIC count
+sh_uint64 sh_lapic_get_lapic_count();
+#define SH_LAPIC_IPI_TYPE_NMI 0b100
+#define SH_LAPIC_IPI_TYPE_INIT 0b101
+#define SH_LAPIC_IPI_TYPE_STARTUP 0b110
+#define SH_LAPIC_IPI_TYPE_FIXED 0b000
+#define SH_LAPIC_IPI_DESTINATION_SPECIFIC (0b00<<18)
+#define SH_LAPIC_IPI_DESTINATION_SELF (0b01<<18)
+#define SH_LAPIC_IPI_DESTINATION_ALL (0b10<<18)
+#define SH_LAPIC_IPI_DESTINATION_ALL_EXCLUDING_SELF (0b11<<18)
+#define SH_LAPIC_IPI_NO_DESTINATION (sh_int16)(-1)
+// Return SH_TRUE if LAPIC IPI feature is busy
+sh_bool sh_lapic_ipi_is_busy(sh_lapic_DEVICE *lapic_dev);
+// Return LAPIC id of current core, return -1 if error happened
+sh_int16 sh_lapic_get_current_core();
+// Send a fixed IPI with the specified vector. lapic_dev must be the struct of the current CPU.
+// If destination_mode!=SH_LAPIC_IPI_DESTINATION_SPECIFIC, target_lapic_id must be SH_LAPIC_IPI_NO_DESTINATION
+SH_STATUS sh_lapic_send_fixed_ipi(sh_lapic_DEVICE *lapic_dev,sh_uint8 vector,sh_uint32 destination_mode,sh_int16 target_lapic_id);
+// Send any IPI other than a fixed IPI to specified destination. lapic_dev must be the struct of the current CPU.
+// ipi_type must be either SH_LAPIC_IPI_TYPE_INIT, SH_LAPIC_IPI_TYPE_STARTUP or SH_LAPIC_IPI_TYPE_NMI
+// If ipi_type is SH_LAPIC_IPI_TYPE_STARTUP, start_address must contain the starting address. Address constraint (compatible with 16 bits mode) are checked.
+// If ipi_type isn't SH_LAPIC_IPI_TYPE_STARTUP, start_address must be zero.
+// If destination_mode!=SH_LAPIC_IPI_DESTINATION_SPECIFIC, target_lapic_id must be SH_LAPIC_IPI_NO_DESTINATION
+SH_STATUS sh_lapic_send_ipi(sh_lapic_DEVICE *lapic_dev,sh_uint32 ipi_type,sh_uint32 destination_mode,sh_int16 target_lapic_id,sh_page_PHYSICAL_ADDRESS start_address);
+// Parse a LAPIC DevS query
+SH_STATUS sh_lapic_devs_query(char *sub_path,sh_devs_RESULT *result);
+#endif

shelter/lib/include/devs/devs.h

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_DEVS_H
+#define SH_LIB_DEVS_H
+#include "std/status.h"
+#include "std/type.h"
+#include "std/string.h"
+// DevS result type enum
+enum sh_devs_RESULT_TYPE {
+  SH_DEVS_LAPIC,
+  SH_DEVS_IOAPIC,
+  SH_DEVS_VALUE,
+  SH_DEVS_BOOL
+};
+// DevS result structure
+typedef struct {
+  enum sh_devs_RESULT_TYPE type;
+  sh_uint64 value;
+} sh_devs_RESULT;
+// Parse a DevS query
+SH_STATUS sh_devs_query(char *path,sh_devs_RESULT *result);
+#endif

shelter/lib/include/devs/input/event.h

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_EVENT_H
+#define SH_LIB_EVENT_H
+#include "std/type.h"
+// Events types
+typedef sh_uint8 sh_event_TYPE;
+#define SH_EVENT_TYPE_PS2_NORMAL 0U
+#define SH_EVENT_TYPE_PS2_E0 1U
+#define SH_EVENT_TYPE_KBD_CONTEXT 2U
+#define SH_EVENT_TYPE_KBD_PAUSE 3U
+// Keyboard events context flags
+#define SH_KBD_EVENT_SHIFT_ACTIVE (1u<<0)
+#define SH_KBD_EVENT_WIN_ACTIVE (1u<<1)
+#define SH_KBD_EVENT_LEFT_ACTIVE (1u<<1)
+#define SH_KBD_EVENT_RIGHT_ACTIVE (1u<<0)
+#define SH_KBD_EVENT_NUMLOCK_ACTIVE (1u<<0)
+#define SH_KBD_EVENT_CAPSLOCK_ACTIVE (1u<<1)
+// Keyboard contexts key scancodes
+#define SH_KBD_CONTEXT_LSHIFT 0U
+#define SH_KBD_CONTEXT_RSHIFT 1U
+#define SH_KBD_CONTEXT_LCTRL 2U
+#define SH_KBD_CONTEXT_RCTRL 3U
+#define SH_KBD_CONTEXT_LALT 4U
+#define SH_KBD_CONTEXT_RALT 5U
+#define SH_KBD_CONTEXT_WIN 6U
+#define SH_KBD_CONTEXT_NUMLOCK 7U
+#define SH_KBD_CONTEXT_CAPSLOCK 8U
+// Keyboard event structure
+typedef struct {
+  sh_uint16 scancode;
+  sh_bool pressed;
+  sh_uint8 context_shift_win;
+  sh_uint8 context_alt;
+  sh_uint8 context_ctrl;
+  sh_uint8 context_lock_status;
+  sh_uint8 event_type;
+  sh_uint64 timestamp; // tsc
+} sh_kbd_EVENT;
+#endif

shelter/lib/include/devs/input/kbd.h

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_KBD_H
+#define SH_LIB_KBD_H
+#include "std/stdlib.h"
+#include "devs/input/event.h"
+// Keyboard driver handle structure, driver handles should only be owned by keyboards drivers
+typedef struct sh_kbd_DRIVER_HANDLE sh_kbd_DRIVER_HANDLE;
+// Keyboard consumer handle structure, used for requests made by consumer
+typedef struct sh_kbd_CONSUMER_HANDLE sh_kbd_CONSUMER_HANDLE;
+// Keyboard device structure
+typedef struct {
+  sh_uint8 kbd_id;
+  sh_queue_KBD_EVENT *events_queue;
+  sh_bool present;
+  sh_bool ver_maj;
+  sh_bool ver_num;
+  sh_bool shift;
+  sh_bool alt;
+  sh_bool ctrl;
+  sh_bool win;
+  sh_SPIN_LOCK spinlock;
+} sh_kbd_DEVICE;
+// Initialize Keyboard input subsystem, should only be called one time
+SH_STATUS sh_kbd_init_devs();
+// Register the PS2 keyboard, completing the provided handle.
+SH_STATUS sh_kbd_register_ps2(sh_bool is_present,sh_kbd_DRIVER_HANDLE **handle);
+// Register any others keyboard, completing the provided handle, that should be used only by the keyboard driver for using the keyboard subsystem API
+SH_STATUS sh_kbd_register(sh_bool is_present,sh_kbd_DRIVER_HANDLE **handle);
+#define SH_KBD_FLAG_PRESENT 0U
+#define SH_KBD_FLAG_VER_MAJ 1U
+#define SH_KBD_FLAG_VER_NUM 2U
+#define SH_KBD_FLAG_SHIFT 3U
+#define SH_KBD_FLAG_ALT 4U
+#define SH_KBD_FLAG_CTRL 5U
+#define SH_KBD_FLAG_WIN 6U
+// Set any flag in the sh_kbd_DEVICE struct, given that a correct handle has been provided
+SH_STATUS sh_kbd_set_flag(sh_kbd_DRIVER_HANDLE *handle,sh_uint8 flag,sh_bool value);
+// Push a keyboard event on the keyboard queue, given that a correct handle has been provided
+SH_STATUS sh_kbd_push_events(sh_kbd_DRIVER_HANDLE *handle,sh_kbd_EVENT *event);
+// Keyboard device enumeration structure
+typedef struct {
+  sh_uint64 bitmap[4];
+} sh_kbd_ENUMERATION;
+// Enumerate all keyboard devices id
+SH_STATUS sh_kbd_enumerate_devices(sh_kbd_ENUMERATION *enumeration);
+// Return a valid consumer handle for the provided keyboard device id
+SH_STATUS sh_kbd_get_handle(sh_uint8 kbd_id,sh_kbd_CONSUMER_HANDLE **handle);
+// Destroy the provided consumer handle and set the pointer to SH_NULLPTR
+SH_STATUS sh_kbd_destroy_handle(sh_kbd_CONSUMER_HANDLE **handle);
+// Read any flag in the sh_kbd_DEVICE struct, given that a correct handle has been provided. Accept either a driver or consumer handle, but fail if both handle are provided
+SH_STATUS sh_kbd_read_flag(sh_kbd_DRIVER_HANDLE *d_handle,sh_kbd_CONSUMER_HANDLE *c_handle,sh_uint8 flag,sh_bool *value);
+#endif

shelter/lib/include/devs/input/ps2.h

@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_PS2_H
+#define SH_LIB_PS2_H
+#include "std/stdlib.h"
+#include "devs/input/event.h"
+#include "devs/input/kbd.h"
+// Port macros
+#define SH_PS2_PORT_DATA 0x60
+#define SH_PS2_PORT_COMMAND 0x64
+// Status byte bits
+#define SH_PS2_STATUS_OBF 0b1
+#define SH_PS2_STATUS_IBF 0b10
+#define SH_PS2_STATUS_MOUSE_DATA 0b100000
+#define SH_PS2_STATUS_TIMEOUT 0b1000000
+#define SH_PS2_STATUS_PARITY 0b10000000
+// Config byte bits
+#define SH_PS2_CONFIG_PORT1_IRQ 0b1
+#define SH_PS2_CONFIG_PORT2_IRQ 0b10
+#define SH_PS2_CONFIG_PORT1_CLOCK_DISABLED 0b10000
+#define SH_PS2_CONFIG_PORT2_CLOCK_DISABLED 0b100000
+#define SH_PS2_CONFIG_TRANSLATION 0b1000000
+// PS2 controller commands macros
+#define SH_PS2_COMMAND_READ_CONFIG 0x20
+#define SH_PS2_COMMAND_WRITE_CONFIG 0x60
+#define SH_PS2_COMMAND_PS2_SELF_TEST 0xAA
+#define SH_PS2_COMMAND_PORT1_TEST 0xAB
+#define SH_PS2_COMMAND_PORT2_DISABLE 0xA7
+#define SH_PS2_COMMAND_PORT2_ENABLE 0xA8
+#define SH_PS2_COMMAND_PORT2_TEST 0xA9
+#define SH_PS2_COMMAND_PORT1_DISABLE 0xAD
+#define SH_PS2_COMMAND_PORT1_ENABLE 0xAE
+#define SH_PS2_COMMAND_READ_OUTPUT 0xD0
+#define SH_PS2_COMMAND_WRITE_OUTPUT 0xD1
+#define SH_PS2_COMMAND_WRITE_PORT2 0xD4
+// Self test results macros
+#define SH_PS2_SELF_TEST_SUCCESS 0x55
+#define SH_PS2_SELF_TEST_FAIL 0xFC
+#define SH_PS2_PORTS_SELF_TEST_SUCCESS 0x00
+// PS2 keyboard commands macros
+#define SH_PS2_KBD_COMMAND_SET_LEDS 0xED
+#define SH_PS2_KBD_COMMAND_ECHO 0xEE
+#define SH_PS2_KBD_COMMAND_SC_SET 0xF0
+#define SH_PS2_KBD_COMMAND_IDENTIFY 0xF2
+#define SH_PS2_KBD_COMMAND_ENABLE_SCANNING 0xF4
+#define SH_PS2_KBD_COMMAND_DISABLE_SCANNING 0xF5
+#define SH_PS2_KBD_COMMAND_DEFAULTS 0xF6
+#define SH_PS2_KBD_COMMAND_RESET 0xFF
+// Leds bits
+#define SH_PS2_KBD_LEDS_SCROLL_LOCK 0b1
+#define SH_PS2_KBD_LEDS_NUM_LOCK 0b10
+#define SH_PS2_KBD_LEDS_CAPS_LOCK 0b100
+// Scancodes (SC) sets
+#define SH_PS2_KBD_SC_SET_CURRENT 0
+#define SH_PS2_KBD_SC_SET_1 1
+#define SH_PS2_KBD_SC_SET_2 2
+#define SH_PS2_KBD_SC_SET_3 3
+// Keyboard response macros
+#define SH_PS2_KBD_ACK 0xFA
+#define SH_PS2_KBD_RESEND 0xFE
+#define SH_PS2_KBD_BAT_SUCCESS 0xAA
+#define SH_PS2_KBD_BAT_FAIL 0xFC
+#define SH_PS2_KBD_ECHO_REPLY 0xEE
+// Return SH_TRUE if data port contain useful datas to read
+inline sh_bool sh_ps2_output_ready() {
+  return sh_asm_inb(SH_PS2_PORT_COMMAND) & SH_PS2_STATUS_OBF;
+}
+// Return SH_TRUE if controller isn't ready for any output
+inline sh_bool sh_ps2_cant_write() {
+  return sh_asm_inb(SH_PS2_PORT_COMMAND) & SH_PS2_STATUS_IBF;
+}
+// Keyboard command struct
+typedef struct {
+  sh_uint8 command;
+  sh_uint8 data;
+  sh_bool has_data;
+} sh_ps2_KBD_COMMAND;
+// Read status byte
+inline sh_uint8 sh_ps2_read_status() {
+  return sh_asm_inb(SH_PS2_PORT_COMMAND);
+}
+// Read config byte
+inline sh_uint8 sh_ps2_read_config() {
+  while (sh_ps2_cant_write());
+  sh_asm_outb(SH_PS2_PORT_COMMAND,SH_PS2_COMMAND_READ_CONFIG);
+  while (!sh_ps2_output_ready());
+  return sh_asm_inb(SH_PS2_PORT_DATA);
+}
+// Write config byte
+inline void sh_ps2_write_config(sh_uint8 config) {
+  while (sh_ps2_cant_write());
+  sh_asm_outb(SH_PS2_PORT_COMMAND,SH_PS2_COMMAND_WRITE_CONFIG);
+  while (sh_ps2_cant_write());
+  sh_asm_outb(SH_PS2_PORT_DATA,config);
+}
+// PS2 IRQ1 handler
+void sh_ps2_irq1_handler();
+// Send a keyboard command and wait for it to finish
+SH_STATUS sh_ps2_send_keyboard_command_wait(sh_uint8 cmd,sh_uint8 data,sh_bool has_data);
+// Initialize the PS2 driver
+SH_STATUS sh_ps2_driver_init();
+// Disable scanning
+SH_STATUS sh_ps2_disable_scanning();
+// Enable scanning
+SH_STATUS sh_ps2_enable_scanning();
+#endif