Vystem 0.2

shelter/lib/include/cpu/ap.h

@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_AP_H
+#define SH_LIB_AP_H
+#include "std/status.h"
+#include "std/type.h"
+#include "memory/memory.h"
+#include "irq/gdt.h"
+#include "irq/idt.h"
+#include "devs/apic/lapic.h"
+#define SH_AP_AP_TRAMPOLINE 0x7000
+#define SH_AP_GDT_32_PA 0x8000
+#define SH_AP_BOOTSTRAP_PA 0x9000
+#define SH_AP_TRAMPOLINE_PAYLOAD 0xA000
+#define SH_AP_STATE_PENDING 0x00
+#define SH_AP_STATE_NO_LAPIC 0x01
+#define SH_AP_STATE_OK 0x02
+// Fill the 32 bits GDT used by AP trampoline
+SH_STATUS sh_ap_load_gdt_32();
+// AP boostrap structure, shared with each AP
+#pragma pack(1)
+typedef struct {
+  sh_page_PHYSICAL_ADDRESS lapic_base_pa;
+  sh_page_VIRTUAL_ADDRESS c_entry_point_va;
+  sh_page_PHYSICAL_ADDRESS page_table_pa;
+  sh_page_VIRTUAL_ADDRESS cpu_struct_base_area;
+  sh_page_VIRTUAL_ADDRESS shared_gdt_64_va;
+  sh_gdt_GDTR gdt_64_gdtr;
+  sh_idt_IDT *idt;
+} sh_ap_AP_BOOTSTRAP;
+#pragma pack()
+// Per-CPU structure, one for each AP
+#pragma pack(1)
+typedef struct {
+  sh_uint64 cpu_id;
+  sh_uint32 bytes_outputed;
+  sh_bool timer_state;
+  char *temp_buffer;
+  sh_uint64 temp_buffer_size;
+} sh_ap_PER_CPU;
+#pragma pack()
+// CPU structure, one for each AP
+#pragma pack(1)
+typedef struct {
+  sh_page_VIRTUAL_ADDRESS c_entry_point_stack_top_va;
+  sh_uint32 lapic_id; // just for the tranpoline to confirm it has found his own struct
+  sh_uint16 tss_selector;
+  sh_ap_PER_CPU *per_cpu;
+} sh_ap_CPU_STRUCT;
+#pragma pack()
+// Allocate each sets of stacks for each TSS and each C stack, create each TSS entry, create global GDT64, create the CPU structure area, create and fill each CPU structure, create the AP bootstrap structure and place it correctly
+SH_STATUS sh_ap_prepare_for_smp_launch(sh_lapic_DEVICE **lapic_dev_array,sh_uint64 max_lapic_id,sh_uint64 expected_lapic_found,sh_conf_BOOT_CONFIG *boot_config,sh_idt_IDT *idt);
+// AP C entry point
+void sh_ap_entry_point();
+// Start AP boot procedure
+SH_STATUS sh_ap_start_ap_boot_procedure(sh_conf_BOOT_CONFIG *boot_config);
+#endif

shelter/lib/include/cpu/asm.h

@@ -3,14 +3,17 @@
 #define SH_LIB_ASM_H
 #include "std/type.h"
 #include "std/status.h"
+#include "irq/gdt.h"
+#include "irq/tss.h"
+#include "irq/idt.h"
 // inb instruction wrapper
-static inline sh_uint8 sh_asm_inb(sh_uint16 port) {
+inline sh_uint8 sh_asm_inb(sh_uint16 port) {
   sh_uint8 val;
   __asm__ volatile ("inb %1, %0":"=a"(val):"Nd"(port));
   return val;
 }
 // outb instruction wrapper
-static inline void sh_asm_outb(sh_uint16 port,sh_uint8 val) {
+inline void sh_asm_outb(sh_uint16 port,sh_uint8 val) {
   __asm__ volatile ("outb %0, %1"::"a"(val),"Nd"(port));
 }
 // rdtsc instruction wrapper
@@ -23,4 +26,44 @@ static inline sh_uint64 sh_asm_rdtsc() {
 static inline void sh_asm_invlpg(void *addr) {
   __asm__ volatile ("invlpg (%0)"::"r"(addr):"memory");
 }
+// lgdt instruction wrapper
+static inline void sh_asm_lgdt(sh_gdt_GDTR gdtr) {
+  __asm__ volatile ("lgdt %0"::"m"(gdtr):"memory");
+}
+// ltr instruction wrapper
+static inline void sh_asm_ltr(sh_uint16 tss_selector) {
+  __asm__ volatile ("ltr %0"::"r"(tss_selector):"memory");
+}
+// lidt instruction wrapper
+static inline void sh_asm_lidt(sh_idt_IDTR idtr) {
+  __asm__ volatile ("lidt %0"::"m"(idtr):"memory");
+}
+// sidt instruction wrapper
+static inline void sh_asm_sidt(sh_idt_IDTR* idtr) {
+  __asm__ volatile ("sidt %0":"=m"(*idtr)::"memory");
+}
+// sti instruction wrapper
+static inline void sh_asm_sti() {
+  __asm__ volatile ("sti");
+}
+// cli instruction wrapper
+static inline void sh_asm_cli() {
+  __asm__ volatile ("cli");
+}
+// cpuid instruction wrapper
+static inline void sh_asm_cpuid(sh_uint32 leaf,sh_uint32 subleaf,sh_uint32 *eax,sh_uint32 *ebx,sh_uint32 *ecx,sh_uint32 *edx){
+  __asm__ volatile ("cpuid":"=a"(*eax),"=b"(*ebx),"=c"(*ecx),"=d"(*edx):"a"(leaf),"c"(subleaf));
+}
+// mfence instruction wrapper
+inline void sh_asm_mfence() {
+  __asm__ volatile("mfence":::"memory");
+}
+// lfence instruction wrapper
+inline void sh_asm_lfence() {
+  __asm__ volatile("lfence":::"memory");
+}
+// sfence instruction wrapper
+inline void sh_asm_sfence() {
+  __asm__ volatile("sfence":::"memory");
+}
 #endif

shelter/lib/include/cpu/pic.h

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_PIC_H
+#define SH_LIB_PIC_H
+#include "std/stdlib.h"
+#define SH_PIC1_CMD 0x20
+#define SH_PIC1_DATA 0x21
+#define SH_PIC2_CMD 0xA0
+#define SH_PIC2_DATA 0xA1
+// Remap all PIC interrupts on interrupts vectors 32 to 47, leave only IRQ0 enabled
+void sh_pic_remap();
+// Unmask a PIC interrupt
+void sh_pic_unmask(sh_uint8 irq);
+// Mask a PIC interrupt
+void sh_pic_mask(sh_uint8 irq);
+// Send EOI to PIC
+void sh_pic_send_eoi(sh_uint8 irq);
+#endif

shelter/lib/include/cpu/pit.h

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: MPL-2.0
+#ifndef SH_LIB_PIT_H
+#define SH_LIB_PIT_H
+#include "std/stdlib.h"
+// Set PIT frequency
+void sh_pit_set_frequency(sh_uint64 hz);
+#endif

shelter/lib/include/cpu/tsc.h

@@ -4,6 +4,7 @@
 #include "std/type.h"
 #include "std/status.h"
 #include "cpu/asm.h"
+#include "devs/devs.h"
 typedef sh_uint64 sh_tsc_TSC_VALUE;
 // Reas TSC register.
 static inline sh_tsc_TSC_VALUE sh_tsc_read_tsc() {
@@ -15,4 +16,16 @@ SH_STATUS sh_tsc_init_tsc();
 sh_tsc_TSC_VALUE sh_tsc_get_kernel_init_tsc();
 // Return kernel current tsc.
 sh_tsc_TSC_VALUE sh_tsc_get_kernel_current_tsc();
+// Estimate CPU frequency using TSC and PIT
+sh_uint64 sh_tsc_estimate_cpu_freq();
+// Load CPU frequency
+void sh_tsc_load_cpu_freq(sh_uint64 cpu_freq);
+// Detect if CPUID provide hypervisor bit
+sh_bool sh_tsc_has_hypervisor();
+// Detect if CPUID provide TSC constant bit
+sh_bool sh_tsc_is_tsc_constant();
+// Return CPUID CPU frequence if available
+SH_STATUS sh_tsc_get_cpu_freq_cpuid(sh_uint64 *freq);
+// Parse a TSC DevS query
+SH_STATUS sh_tsc_devs_query(char *sub_path,sh_devs_RESULT *result);
 #endif